Rev 1.6

vicorpower.com

Page 4 of 26

09/2016

800 927.9474

PI3749-x0

Pin Description

Pin Number

Pin Name

Description

1-2,G-K

Input voltage and sense node for UVLO, OVLO and feed forward compensation.

4-5,G-K

VS1

Input side switching node and ZVS sense node for power switches.

10-11,G-K

VS2

Output side switching node and ZVS sense node for power switches.

13-14,G-K

and internal signals.

1E

VDR

Internal 5.1V supply for gate drivers and internal logic; not for external use.

1D

PGD

Fault & Power Good indicator. PGD pulls low when the regulator is not operating or if EAIN is less

than 1.4V.

1C

SYNCO

Synchronization output. Outputs a high signal for ½ of the programmed switching period at the beginning

of each switching cycle, for synchronization of other regulators.

1B

SYNCI

Synchronization input. When a falling edge synchronization pulse is detected, the PI3749-x0 will delay

the start of the next switching cycle until the next falling edge sync pulse arrives, up to a maximum

delay of two times the programmed switching period. If the next pulse does not arrive within two

times the programmed switching period, the controller will leave sync mode and start a switching cycle

automatically. Connect to SGND when not in use.

1A

ADR1

2A

ADR0

3A

SCL

4A

SDA

5A

EN

Regulator Enable control. Asserted high or left floating = regulator enabled;

Asserted low, regulator output disabled.

6A

TRK

Soft-start and track input. An external capacitor may be connected between TRK pin and SGND to

decrease the rate of output rise during soft-start.

7A

TEST5

For factory use only. Connect to SGND in application.

8A

COMP

Error amp compensation dominant pole. Connect a capacitor between COMP and SGND to set the control

loop dominant pole.

9A

VSN

General purpose amplifier inverting input

10A

VSP

General purpose amplifier non-inverting input

11A

VDIFF

General Purpose amplifier output. When unused connect VDIFF to VSN and VSP to SGND.

12A

EAIN

Error amplifier inverting input and sense for PGD. Connect by resistive divider to the output.

13A

EAO

Transconductance error amplifier output, PWM input and external connection for load sharing.

Connect a capacitor between EAO and SGND to set the control loop high frequency pole.

14A

IMON

High side current sense amplifier output

14D

ISN

High side current sense amplifier negative input

14E

ISP

High side current sense amplifier positive input

10-14,B + 10-12,C-E

SGND

Signal ground. Internal logic and analog ground for the regulator. SGND and PGND are star connected

within the regulator package.

2-9,B-E + 7-8,F-K

PGND

regulator package.