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BD71L4L-1 Datasheet(PDF) 7 Page - Rohm |
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BD71L4L-1 Datasheet(HTML) 7 Page - Rohm |
7 / 18 page 7/14 BD71L4L-1 series TSZ02201-0R7R0G300030-1-2 © 2016 ROHM Co., Ltd. All rights reserved. 08.Jun.2016.Rev.005 www.rohm.com TSZ22111・15・001 Application Information 1. Explanation of Operation The detection and release voltages are used as threshold voltages. When the voltage applied to VDD pin reaches the appropriate threshold voltage, OUT pin voltage switches from either “High” to “Low” or from “Low” to “High”. Please refer to the Timing Waveform and Electrical Characteristics for information on hysteresis. Because the BD71L4L-1 uses an open drain output type, it is necessary to connect a pull-up resistor to VDD or another power supply if needed [The output “High” voltage (VOUT) in this case becomes VDD or the voltage of the other power supply]. Figure 14. Internal Block Diagram 2. Timing Waveform Example: the following shows the relationship between the input voltage (VDD) and the output voltage (VOUT) when the input power supply voltage (VDD) swept up and down (the circuit is shown in Figure 14). 1 When the power supply is turned on, the output is unstable from after over the operating limit voltage (VOPL) until tPLH. Therefore it is possible that the reset signal is not outputted when the rise time of VDD is faster than tPLH. 2 When VDD is greater than VOPL but less than the reset detection voltage (VDET), the output voltage will switch to High. 3 If VDD exceeds the reset detection voltage (VDET) when the power supply is powered up, VOUT switches from H to L (with a delay of tPHL). 4 If VDD drops below the release voltage (VDET - ∆ VDET) when the power supply is powered down, VOUT switches to H (with a delay of tPLH). 5 The potential difference between the detection voltage and the release voltage is known as the hysteresis width (∆VDET). Figure 15. Timing Waveform Vref R1 R2 VDD GND Q1 VOUT R3 RL VDD VDET VOPL 0V VOUT tPHL tPHL tPLH VOL VOH VDET -ΔVDET tPLH ② ③ ④ ⑤ ① |
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