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NBSG72AMNG Datasheet(PDF) 3 Page - ON Semiconductor |
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NBSG72AMNG Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 16 page NBSG72A http://onsemi.com 3 Q0 Q0 LOW D0 HIGH D1 LOW D0 HIGH D1 SELA Q0 Figure 2. Logic/Block Diagram LOW LOW HIGH HIGH SELB D0 D0 D1 D1 Q1 VTD0 D0 SELA SELB OLS Q1 22 22 2 2 2 2 2 2 VCC VEE + 50 W 50 W 75 k W 75 k W Table 2. TRUTH TABLE Q1 D0 50 W VTD1 D1 D1 50 W Table 3. OUTPUT LEVEL SELECT (OLS) OLS Output Amplitude (VOUTPP) OLS Sensitivity VCC 800 mV OLS − 75 mV VCC − 0.4 V 200 mV OLS ± 150 mV VCC − 0.8 V 600 mV OLS ± 100 mV VCC − 1.2 V 0 OLS ± 75 mV VEE (Note 3) 400 mV OLS ± 100 mV FLOAT 600 mV N/A 3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. Table 4. INTERFACING OPTIONS Interfacing Options Connections CML Connect VTD0 and VTD1 to VCC LVDS VTD0 and VTD1 Should Be Left Floating. AC−COUPLED Bias VTD0 and VTD1 Inputs within Common Mode Range (VIHCMR) RSECL, PECL, NECL Standard ECL Termination Techniques LVCMOS / LVTTL The external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. |
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