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TN0610N3-GP002 Datasheet(PDF) 1 Page - Supertex, Inc

Part # TN0610N3-GP002
Description  N-Channel Enhancement-Mode Vertical DMOS FET
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Manufacturer  SUTEX [Supertex, Inc]
Direct Link  http://www.supertex.com
Logo SUTEX - Supertex, Inc

TN0610N3-GP002 Datasheet(HTML) 1 Page - Supertex, Inc

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Supertex inc.
Supertex inc.
www.supertex.com
Doc.# DSFP-TN0610
B080813
TN0610
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
SiTN
0610
YYWW
Features
Low threshold - 2.0V max.
High input impedance
Low input capacitance - 100pF typical
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
N-Channel Enhancement-Mode
Vertical DMOS FET
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
BV
DSS
Drain-to-gate voltage
BV
DGS
Gate-to-source voltage
±20V
Operating and storage temperature
-55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
TO-92
GATE
SOURCE
DRAIN
TO-92
Product Marking
Pin Configuration
Package may or may not include the following marks: Si or
Ordering Information
Part Number
Package Option
Packing
TN0610N3-G
TO-92
1000/Bag
TN0610N3-G P002
TO-92
2000/Reel
TN0610N3-G P003
TN0610N3-G P005
TN0610N3-G P013
TN0610N3-G P014
Product Summary
BV
DSS/BVDGS
R
DS(ON)
(max)
I
D(ON)
(min)
V
GS(th)
(max)
100V
1.5Ω
3.0A
2.0V
Typical Thermal Resistance
Package
θ
ja
TO-92
132OC/W
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.


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