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CS8420 Datasheet(PDF) 7 Page - Cirrus Logic |
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CS8420 Datasheet(HTML) 7 Page - Cirrus Logic |
7 / 80 page CS8420 DS245PP2 7 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (T A = 25 °C; VA+ = VD+ = 5V ±5%, Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20 pF) Notes: 5. The active edges of ISCLK and OSCLK are programmable. 6. The polarity of ILRCK and OLRCK is programmable. 7. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK has changed. 8. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed. Parameter Symbol Min Typ Max Units OSCLK Active Edge to SDOUT Output Valid (Note 5) tdpd -- 20 ns SDIN Setup TIme Before ISCLK Active Edge (Note 5) tds 20 - - ns SDIN Hold Time After ISCLK Active Edge (Note 5) tdh 20 - - ns Master Mode O/RMCK to I/OSCLK active edge delay (Note 5) tsmd 0- 10 ns O/RMCK to I/OLRCK delay (Note 6) tlmd 0- 10 ns I/OSCLK and I/OLRCK Duty Cycle - 50 - % Slave Mode I/OSCLK Period tsckw 36 - - ns I/OSCLK Input Low Width tsckl 14 - - ns I/OSCLK Input High Width tsckh 14 - - ns I/OSCLK Active Edge to I/OLRCK Edge (Note 5,6,7) tlrckd 20 - - ns I/OLRCK Edge Setup Before I/OSCLK Active Edge (Note 5,6,8) tlrcks 20 - - ns sckh sckl sckw t t t tdpd SDOUT (input) (input) SDIN dh t ds t lrcks t lrckd t ISCLK OSCLK ILRCK OLRCK ISCLK OSCLK ILRCK OLRCK (output) (output) RMCK OMCK (input) t smd t lmd Figure 1. Audio Ports Master Mode Timing Figure 2. Audio Ports Slave Mode and Data I/O Timing |
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