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CAT5419WI10 Datasheet(PDF) 5 Page - ON Semiconductor

Part # CAT5419WI10
Description  Dual Digital Potentiometer (POT)
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
Units
fSCL
Clock Frequency
400
kHz
TI (Note 8)
Noise Suppression Time Constant at SCL, SDA Inputs
50
ns
tAA
SLC Low to SDA Data Out and ACK Out
0.9
ms
tBUF (Note 8)
Time the bus must be free before a new transmission can start
1.2
ms
tHD:STA
Start Condition Hold Time
0.6
ms
tLOW
Clock Low Period
1.2
ms
tHIGH
Clock High Period
0.6
ms
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
ms
tHD:DAT
Data in Hold Time
0
ns
tSU:DAT
Data in Setup Time
100
ns
tR (Note 8)
SDA and SCL Rise Time
0.3
ms
tF (Note 8)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
0.6
ms
tDH
Data Out Hold Time
50
ns
Table 8. POWER UP TIMING (Note 8) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 9. WRITE CYCLES LIMITS (Note 9)
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
9. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Table 10. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
NEND (Note 10)
Endurance
MIL−STD−883, Test Method 1033
1,000,000
Cycles/Byte
TDR (Note 10)
Data Retention
MIL−STD−883, Test Method 1008
100
Years
VZAP (Note 10)
ESD Susceptibility
MIL−STD−883, Test Method 3015
2,000
Volts
ILTH (Notes 10, 11)
Latch-up
JEDEC Standard 17
100
mA
10.This parameter is tested initially and after a design or process change that affects the parameter.
11. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.


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