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CAT5411YI00 Datasheet(PDF) 4 Page - ON Semiconductor |
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CAT5411YI00 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 14 page CAT5411 http://onsemi.com 4 DEVICE OPERATION The CAT5411 is two resistor arrays integrated with SPI serial interface logic, two 6-bit wiper control registers and eight 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the SPI bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer’s non-volatile data registers. Also, the device can be instructed to operate in an “increment/decrement” mode. SERIAL BUS PROTOCOL The CAT5041 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT5411 to interface directly with many of today’s popular microcontrollers. The CAT5041 contains an 8-bit instruction register. The instruction set and the operation codes are detailed in the instruction set Table 12. After the device is selected with CS going low the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. Table 2. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter Reference Test Method Min Typ Max Units NEND (Note 1) Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte TDR (Note 1) Data Retention MIL−STD−883, Test Method 1008 100 Years VZAP (Note 1) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 Volts ILTH (Note 1) Latch-up JEDEC Standard 17 100 mA 1. This parameter is tested initially and after a design or process change that affects the parameter. Table 3. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Temperature Under Bias −55 to +125 C Storage Temperature Range −65 to +150 C Voltage to any Pins with Respect to VSS (Notes 2, 3) −2.0 to VCC +2.0 V VCC with Respect to GND −2.0 to +7.0 V Package Power Dissipation Capability (TA = 25C) 1.0 W Lead Soldering Temperature (10 s) 300 C Wiper Current 12 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. 3. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V. Table 4. RECOMMENDED OPERATING CONDITIONS Parameters Ratings Units VCC +2.5 to 6.0 V Industrial Temperature −40 to +85 C |
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