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XC2286M-56FxxL Datasheet(PDF) 8 Page - Infineon Technologies AG |
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XC2286M-56FxxL Datasheet(HTML) 8 Page - Infineon Technologies AG |
8 / 146 page XC2287M, XC2286M, XC2285M XC2000 Family / Base Line Summary of Features Data Sheet 8 V2.1, 2011-07 – Two Synchronizable A/D Converters with a total of up to 24 channels, 10-bit resolution, conversion time below 1 μs, optional data preprocessing (data reduction, range check), broken wire detection – Up to 8 serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS interface – On-chip MultiCAN interface (Rev. 2.0B active) with up to 256 message objects (Full CAN/Basic CAN) on up to 6 CAN nodes and gateway functionality – On-chip system timer and on-chip real time clock • Up to 12 Mbytes external address space for code and data – Programmable external bus characteristics for different address ranges – Multiplexed or demultiplexed external address/data buses – Selectable address bus width – 16-bit or 8-bit data bus width – Four programmable chip-select signals – Hold- and hold-acknowledge bus arbitration support • Single power supply from 3.0 V to 5.5 V • Power reduction and wake-up modes with flexible power management • Programmable watchdog timer and oscillator watchdog • Up to 119 general purpose I/O lines • On-chip bootstrap loaders • Supported by a full range of development tools including C compilers, macro- assembler packages, emulators, evaluation boards, HLL debuggers, simulators, logic analyzer disassemblers, programming boards • On-chip debug support via Device Access Port (DAP) or JTAG interface • 144-pin Green LQFP package, 0.5 mm (19.7 mil) pitch |
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