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SN74V225 Datasheet(PDF) 11 Page - Texas Instruments |
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SN74V225 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 40 page SN74V215, SN74V225, SN74V235, SN74V245 512 × 18, 1024 × 18, 2048 × 18, 4096 × 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional description (continued) Table 4. Status Flags for Standard Mode NUMBER OF WORDS IN FIFO FF PAF HF PAE EF SN74V215 SN74V225 SN74V235 SN74V245 FF PAF HF PAE EF 0 0 0 0 H H H L L 1 to n† 1 to n† 1 to n† 1 to n† H H H L H (n+1) to 256 (n+1) to 512 (n+1) to 1024 (n+1) to 2048 H H H H H 257 to [512–(m+1)]‡ 513 to [1025–(m+1)]‡ 1025 to [2048–(m+1)]‡ 2049 to [4096–(m+1)]‡ H H L H H (512–m) to 511 (1024–m) to 1023 (2048–m) to 2047 (4096–m) to 4095 H L L H H 512 1024 2048 4096 L L L H H † n = Empty offset (SN74V215 n = 63; SN74V225, SN74V235, and SN74V245 n = 127) ‡ m = Full offset (SN74V215 m = 63; SN74V225, SN74V235, and SN74V245 m = 127) PROGRAMMABLE FLAG LOADING Full- and empty-flag offset values can be user programmable. The SN74V215, SN74V225, SN74V235, and SN74V245 have internal registers for these offsets. Default settings are stated in the footnotes of Table 3 and Table 4. Offset values are loaded into the FIFO using the data input lines D0–D11. To load the offset registers, the load (LD) pin and WEN pin must be held low. Data present on D0–D11 is transferred to the empty offset register on the first low-to-high transition of WCLK. By continuing to hold the LD and WEN pins low, data present on D0–D11 is transferred into the full offset register on the next transition of the WCLK. The third transition again writes to the empty offset register. Writing to all offset registers does not have to occur at the same time. One or two offset registers can be written and, then, by bringing the LD pin high, the FIFO is returned to normal read/write operation. When the LD pin and WEN again are set low, the next offset register in sequence is written. The contents of the offset registers can be read on the data output lines Q0–Q11 when the LD pin is set low, and REN is set low. Data then can be read on the next low-to-high transition of RCLK. The first transition of RCLK presents the empty offset value to the data output lines. The next transition of RCLK presents the full offset value. Offset register content can be read in the standard mode only. It cannot be read in the FWFT mode. SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION The SN74V215, SN74V225, SN74V235, and SN74V245 can be configured during the configuration-at-reset cycle (see Table 5) with either asynchronous or synchronous timing for PAE and PAF flags. If asynchronous PAE/PAF configuration is selected (see Table 5), the PAE is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, the PAF is asserted low on the low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. For detailed timing diagrams, see Figure 9 for asynchronous PAE timing and Figure 10 for asynchronous PAF timing. If synchronous PAE/PAF configuration is selected, PAE is asserted and updated on the rising edge of RCLK only, but not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only, but not RCLK. For detailed timing diagrams, see Figure 18 for synchronous PAE timing and Figure 19 for synchronous PAF timing. |
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