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TMS6644148 Datasheet(PDF) 11 Page - Texas Instruments |
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TMS6644148 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 56 page  TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 four-bank row-access operation One of the features of the four-bank operation is access to information on random rows at a higher rate of operation than is possible with a standard DRAM. This is accomplished by activating one of the banks with a row address and, while the data stream is being accessed to/from that bank, activating one of the other banks with other row addresses. When the data stream to / from the first activated bank is complete, the data stream to / from the second activated bank can begin without interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next round of accesses or the entry of new row addresses for other banks which currently are deactivated. In this manner, operation can continue in an interleaved fashion. Figure 29A is an example of four-bank, row-interleaving, read bursts with automatic deactivate with a CAS latency of 3 and a burst length of 8. Figure 29B is an example of four-bank, row-interleaving, read bursts with automatic deactivate with a CAS latency of 3 and a burst length of 4. four-bank column-access operation The availability of four banks allows the access of data from random starting columns between banks at a higher rate of operation. After activating each bank with a row address (ACTV command), A12 – A13 for the four-bank column-access operation can be used to alternate READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all specified timing requirements are met. Figure 30 is an example of four-bank, column-interleaving, read bursts with a CAS latency of 3 and a burst length of 2. bank deactivation (precharge) All banks can be deactivated simultaneously (placed in precharge) by using the DCAB command. A single bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB command except that A10 must be low and A12 – A13 select the bank to be precharged (see Table 1; Figure 27 and Figure 31 provide examples). A bank can also be deactivated automatically by using A10 during a READ or WRT command. If A10 is held high during the entry of a READ or WRT command, the accessed bank, selected by A12 – A13, is automatically deactivated upon completion of the access burst. If A10 is held low during READ- or WRT-command entry, that bank remains active following the burst. The READ and WRT commands with automatic deactivation are denoted as READ-P and WRT-P. See Figure 29A and Figure 29B for examples. chip-select CS (chip-select) can be used to select or deselect the ’664xx4 for command entries, which might be required for multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device does not respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). Using CS does not affect an access burst that is in progress; the DESL command can restrict only RAS, CAS, and W inputs to the ’664xx4. |
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