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ISD-T360SB Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers |
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ISD-T360SB Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers |
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11 / 109 page  1—HARDWARE ISD-T360SB 1-3 ISD 1.2 DESCRIPTION This section provides details of the functional characteristics of the VoiceDSP processor. It is di- vided into the following sections: • Resetting • Clocking • Power-Down Mode • Power and Grounding • Memory Interface • Codec Interface 1.2.1 RESETTING The RESET pin is used to reset the VoiceDSP pro- cessor. On application of power, RESET must be held low for at least tpwr after VCC is stable. This ensures that all on-chip voltages are completely stable before operation. Whenever RESET is applied, it must also remain active for not less than tRST, see Table 1-10 and Table 1-11. During this period, and for 100 ms after, the TST signal must be high. This can be done with a pull-up resistor on the TST pin. The value of MWRDY is undefined during the re- set period, and for 100 ms after. The microcon- troller should either wait before polling the signal for the first time, or the signal should be pulled high during this period. Upon reset, the ENV0 signal is sampled to deter- mine the operating environment. During reset, the EMCS/ENV0 pin is used for the ENV0 input sig- nals. An internal pull-up resistor sets ENV0 to 1. After reset, the same pin is used for EMCS. System Load on ENV0 For any load on the ENV0 pin, the voltage should not drop below VENVh (see Table 1-10 and Table 1-11). If the load on the ENV0 pin causes the current to exceed 10 µA, use an external pull-up resistor to keep the pin at 1. Figure 1-2 shows a recommended circuit for generating a reset signal when the power is turned on. Figure 1-2: Recommended Power-On Reset Circuit 1.2.2 CLOCKING The VoiceDSP processor provides an internal os- cillator that interacts with an external clock source through the X1 and X2/CLKIN pins. Either an external single-phase clock signal, or a crystal oscillator, may be used as the clock source. External Single-Phase Clock Signal If an external single-phase clock source is used, it should be connected to the CLKIN signal as shown in Figure 1-3, and should conform to the voltage-level requirements for CLKIN stated in “ELECTRICAL CHARACTERISTICS” on page 1-18. VCC RESET ISD-T360 VCC VSS |
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