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LM2612BBL Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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LM2612BBL Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 19 page Electrical Characteristics (Continued) Specifications with standard typeface are for T A =TJ = 25˚C, and those in bold face type apply over the full Operating Tem- perature Range (T A =TJ = −25˚C to +85˚C). Unless otherwise specified, PVIN = VDD = EN = SYNC = 3.6V, VID0 = VID1 = 0V. Symbol Parameter Conditions Min Typ Max Units f sync SYNC/MODE Clock Frequency Range (Note 8) 500 1000 kHz F OSC Internal Oscillator Frequency LM2612ABL/ATL, PWM Mode (SYNC = VIN) 468 600 732 kHz LM2612BBL/BTL, PWM Mode (SYNC = VIN) 450 600 750 T min Minimum ON-Time of P FET Switch in PWM Mode 200 nS Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but parameter specifications may not be guaranteed. For guaranteed specifications and associated test conditions, see the Min and Max limits and Conditions in the Electrical Characteristics table. Electrical Characteristics table limits are guaranteed by production testing, design or correlation using standard Statistical Quality Control methods. Typical (Typ) specifications are mean or average values from characterization at 25˚C and are not guaranteed. Note 2: Thermal shutdown will occur if the junction temperature exceeds the 150˚C maximum junction temperature of the device. Note 3: Thermal resistance specified with 2 layer PCB(0.5/0.5 oz. cu). Note 4: The LM2612 is designed for applications where turn-on after system power-up is controlled by the system processor and internal UVLO (Under Voltage LockOut) circuitry is unnecessary. The LM2612 has no UVLO circuitry and should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.8V. Although the LM2612 exhibits safe behavior while enabled at low input voltages, this is not guaranteed. Note 5: The feedback voltage is trimmed at the 1.5V output setting. The other output voltages result from the pin selection of the internal DAC’s divider ratios. The precision for the feedback voltages is ±2%. Note 6: : The hysteresis voltage is the minimum voltage swing on FB that causes the internal feedback and control circuitry to turn the internal PFET switch on and then off during PFM mode. Note 7: Current limit is built-in, fixed, and not adjustable. If the current limit is reached while the output is pulled below about 0.7V, the internal PFET switch turns off for 2.5 µs to allow the inductor current to diminish. Note 8: SYNC driven with an external clock switching between VIN and GND. When an external clock is present at SYNC, the IC is forced to PWM mode at the external clock frequency. The LM2612 synchronizes to the rising edge of the external clock. www.national.com 5 |
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