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CS8416-CZ Datasheet(PDF) 7 Page - Cirrus Logic |
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CS8416-CZ Datasheet(HTML) 7 Page - Cirrus Logic |
7 / 48 page CS8416 DS578PP2 7 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (TA = 25 °C for suffixes ‘CS’ & ’CZ’, TA = -40 to 85 °C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.5 V, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL =20pF) Notes: 5. In Software mode the active edges of OSCLK are programmable. 6. In Software mode the polarity of OLRCK is programmable. 7. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK has changed. 8. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed. Parameter Symbol Min Typ Max Units OSCLK Active Edge to SDOUT Output Valid (Note 5)tdpd - - 15 ns Master Mode RMCK to OSCLK active edge delay (Note 5)tsmd 0 - 10 ns RMCK to OLRCK delay (Note 6)tlmd 0 - 10 ns OSCLK and OLRCK Duty Cycle - 50 - % Slave Mode OSCLK Period tsckw 36 - - ns OSCLK Input Low Width tsckl 14 - - ns OSCLK Input High Width tsckh 14 - - ns OSCLK Active Edge to OLRCK Edge (Notes 5,6,7)tlrckd 10 - - ns OSCLK Edge Setup Before OSCLK Active-Edge (Notes 5,6,8)tlrcks 10 - - ns Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing sckh sckl sckw t t t tdpd SDOUT (input) (input) lrcks t lrckd t OSCLK OLRCK OSC L K OL R C K (output) (output) RM C K t sm d t lm d (o utp ut) |
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