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TMS28F010B-10C5FML Datasheet(PDF) 8 Page - Texas Instruments |
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TMS28F010B-10C5FML Datasheet(HTML) 8 Page - Texas Instruments |
8 / 23 page TMS28F010B 131072 BY 8-BIT FLASH MEMORY SMJS824B – MAY 1995 – REVISED AUGUST 1997 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 command definitions (continued) set-up-erase / erase commands The erase-algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the erase mode, write the set-up-erase command, 20h, into the command register. After the TMS28F010B is in the erase mode, writing a second erase command, 20h, into the command register invokes the erase operation. The erase operation begins on the rising edge of W and ends on the rising edge of the next W. The erase operation requires at least 9.5 ms to complete before the erase-verify command, A0h, can be loaded. Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase operation, the device enters an inactive state and remains inactive until a command is received. program-verify command The TMS28F010B can be programmed sequentially or randomly because it is programmed one byte at a time. Each byte must be verified after it is programmed. The program-verify operation prepares the device to verify the most recently programmed byte. To invoke the program-verify operation, C0h must be written into the command register. The program-verify operation ends on the rising edge of W. While verifying a byte, the TMS28F010B applies an internal margin voltage to the designated byte. If the true data and programmed data match, programming continues to the next designated byte location; otherwise, the byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte programming. erase-verify command All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte can be verified by writing the erase-verify command, A0h, into the command register. This command causes the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on the falling edge of W. The erase-verify operation remains enabled until a command is written to the command register. To determine whether or not all the bytes have been erased, the TMS28F010B applies a margin voltage to each byte. If FFh is read from the byte, all bits in the designated byte have been erased. The erase-verify operation continues until all of the bytes have been verified. If FFh is not read from a byte, an additional erase operation needs to be executed. Figure 2 shows the combination of commands and bus operations for electrically erasing the TMS28F010B. set-up-program / program commands The programming algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the programming mode, write the set-up-program command, 40h, into the command register. The programming operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W, and data is latched internally on the rising edge of W. The programming operation begins on the rising edge of W and ends on the rising edge of the next W pulse. The program operation requires 10 µs for completion before the program-verify command, C0h, can be loaded. Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program operation, the device enters an inactive state and remains inactive until a command is received. reset command To reset the TMS28F010B after set-up-erase command or set-up-program command operations without changing the contents in memory, write FFh into the command register two consecutive times. After executing the reset command, the device defaults to the read mode. |
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