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TMS28F010B-90C5FML Datasheet(PDF) 10 Page - Texas Instruments |
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TMS28F010B-90C5FML Datasheet(HTML) 10 Page - Texas Instruments |
10 / 23 page TMS28F010B 131072 BY 8-BIT FLASH MEMORY SMJS824B – MAY 1995 – REVISED AUGUST 1997 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Bus Operation Command Comments Initialize Address Standby Wait for VPP to ramp to VPPH (see Note A) Initialize pulse count Write Set-Up-Pr ogram Write Data = 40h Write Write Data Valid address / data Standby Wait = 10 µs Write Program- Verify Data = C0h; ends Program operation Standby Wait = 6 µs Read Read byte to verify Programming; compare output to expected output — — — Write Read Data = 00h; resets register for read operations Standby Wait for VPP to ramp to VPPL (see Note B) NOTES: A. Refer to the recommended operating conditions for the value of VPPH. B. Refer to the recommended operating conditions for the value of VPPL. Figure 1. Programming Flowchart: Fastwrite Algorithm Apply VPPL Last Address ? Start Address = 00h VCC = 5 V ± 10%, VPP = 12 V ± 5% Device Passed Increment Address Read and Verify Byte Pass No Yes Yes No Fail X = 1 Write Data X = X + 1 Wait = 10 µs Write Read Command X = 25? Setup Wait = 6 µs Write Program-Verify Command Device Failed Power Down Interactive Mode Apply VPPL Write Set-Up-Program Command |
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