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TDA7565 Datasheet(PDF) 5 Page - STMicroelectronics |
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TDA7565 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 10 page 5/10 TDA7565 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7565 and viceversa takes place through the 2 wires I2C BUS inter- face, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown by fig. 2, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown by fig. 3 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 22). The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock pulse. * Transmitter master ( µP) when it writes an address to the TDA7565 slave (TDA7565) when the µP reads a data byte from TDA7565 ** Receiver slave (TDA7565) when the µP writes an address to the TDA7565 master ( µP) when it reads a data byte from TDA7565 Figure 2. Data Validity on the I2C BUS Figure 3. Figure 4. SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 SCL SDA START I2CBUS STOP D99AU1032 SCL 1 MSB 23789 SDA START ACKNOWLEDGMENT FROM RECEIVER D99AU1033 |
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