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CS8401A-CP Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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CS8401A-CP Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 34 page  may be used to avoid contention between the transmit pointer reading the data and the user up- dating the buffer memory. Besides indicating the byte location being transmitted, the flags indicate the block of memory the part is currently ad- dressing, thereby telling the user which block is free to be written to. Each flag has a correspond- ing mask bit (control register 1) which, when set, allows a transition on the flag to generate a pulse on the interrupt pin. Flag 0 and flag 1 cause in- terrupts on both edges whereas flag 2 causes an interrupt only on the rising edge. Timing and further explanation of the flags can be found in the buffer memory section. The two most significant bits of control register 1, BKST and TRNPT, are used for Transparent Mode operation of the CS8401A. Transparent Mode is used for those applications where it is useful to maintain frame alignment between the received and transmitted audio data signals. In Transparent Mode (TRNPT = "1") the MCK, FSYNC, SCK and SDATA inputs of the CS8401A can be connected to their corresponding outputs of the CS8411. In Trans- parent Mode, FSYNC synchronizes the transmitter and the receiver. The data delay through the CS8401A is set so that three frame delays occur from the input of the CS8411 to the output of the CS8401A. In Transparent Mode, 32 SCK’s are required per subframe. Channel status block alignment between the CS8411 and the CS8401A is accomplished by setting BKST high at the occurrence of the Flag 2 rising edge of the CS8411. If FSYNC is a left/right signal, BKST is sampled once per frame; if FSYNC is a word clock, BKST is sam- pled once per subframe. A low to high transition of BKST (based on two successive internal sam- ples) resets the channel status block boundary to the beginning. Control register 2, shown in Figure 8, contains various system level functions. The two most significant bits, M1 and M0, select the frequency at the MCK pin as shown in Table 1. As an ex- ample, if the audio sample frequency is 44.1 kHz and M0 and M1 are both zero, MCK would then be 128 × the audio sample rate or 5.6448 MHz. The next bit (5) in control register 2, V, indicates the valid- ity of the current audio sample. According to the Figure 4. CS8401A Block Diagram Control and Flags 4 X 8 Buffer Memory 28 X 8 Parity Preamble Timing Mux MCK TXP TXN Serial Port Audio Logic FSYNC SCK SDATA D0-D7 A4-A0 C Bits Control Read Address Generator Interrupt RD/WR CS INT Aux CRC Biphase Mark Encoder Line Driver 7 6 8 21-24, 1-4 9-13 14 16 15 20 17 5 U Bits Validity Prescaler IMCK CS8401A 8 DS60F1 |
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