EM6AB080TSB-5G datasheet(6/62 Pages) ETRON

Part #	EM6AB080TSB-5G

Description	64M x 8 bit DDR Synchronous DRAM (SDRAM

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Manufacturer	ETRON [Etron Technology, Inc.]

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EtronTech

EM6AB080

Etron Confidential

6

Rev.1.1

Dec. /2013

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3

shows the truth table for the operation commands.

Table 3. Truth Table (Note (1), (2))

Command

State

CKEn-1 CKEn DM BA0,1 A10 A0-9, 11-12 CS RAS CAS WE

BankActivate

Idle(3)

H

X

V

Row address

L

H

BankPrecharge

Any

H

X

V

L

X

L

H

L

PrechargeAll

Any

H

X

H

X

L

H

L

Write

Active(3)

H

X

V

L

H

L

Write and AutoPrecharge

Active(3)

H

X

V

H

Column

address

(A0 ~ A9)

L

H

L

Read

Active(3)

H

X

V

L

H

L

H

Read and Autoprecharge

Active(3)

H

X

V

H

Column

address

(A0 ~ A9)

L

H

L

H

Mode Register Set

Idle

H

X

OP code

L

Extended MRS

Idle

H

X

OP code

L

No-Operation

Any

H

X

L

H

Burst Stop

Active(4)

H

X

L

H

L

Device Deselect

Any

H

X

H

X

AutoRefresh

Idle

H

X

L

H

SelfRefresh Entry

Idle

H

L

X

L

H

SelfRefresh Exit

Idle

L

H

X

H

X

(SelfRefresh)

L

H

Idle

H

L

X

H

X

Precharge Power Down Mode

Entry

L

H

Any

L

H

X

H

X

Precharge Power Down Mode

Exit

(PowerDown)

L

H

Active

H

L

X

H

X

Active Power Down Mode Entry

L

V

Any

L

H

X

H

X

Active Power Down Mode Exit

(PowerDown)

L

H

Data Input Mask Disable

Active

H

X

L

X

Data Input Mask Enable

Active

H

X

H

X

Note:

1. V=Valid data, X=Don't Care, L=Low level, H=High level

2. CKEn signal is input level when commands are provided.

CKEn-1 signal is input level one clock cycle before the commands are provided.

3. These are states of bank designated by BA signal.

4. Device state is 2, 4, and 8 burst operation.

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EM6AB080TSB-5G Datasheet(PDF) 6 Page - Etron Technology, Inc.

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