BD8256EFV-ME2 datasheet(9/53 Pages) ROHM

Part #	BD8256EFV-ME2

Description	9ch System Motor Driver For Car AV

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Manufacturer	ROHM [Rohm]

Direct Link	http://www.rohm.com

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TSZ02201-0G1G0BK00030-1-2

4.Apr.2016 Rev.004

www.rohm.com

TSZ22111・15・001

BD8256EFV-M

◆ DAC Register

1. Input / Output Sequence

Enter the register address in the SDI input on the first 4 bits and data for a specific DAC voltage in the next 12 bits.

When specified as REG=02h (address for focus), REG 77h data is output to the SDO.

When specified as REG≠02h (address for non-focus), SDO becomes Hi-Z.

SLV

SCLK

Hi-Z

SDO

D6

D5

D4

D3

D2

D1

D0

D7

SDI

DB

DA

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

C3

C2

C1

C0

Figure 5. 12bit Write / 8bit Read Sequence (when specified as REG=02h)

SLV

SCLK

SDO

Hi-Z

SDI

C1

C0

DB

DA

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

C3

C2

Figure 6. 12bit Write Sequence (when specified as REG≠02h, C3, C2≠1, 1)

2. Address Map (hereinafter register address is referred to as REG)

DAC Register Address Map

REG

NAME

R/W

DB

DA

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Reset

**

00h

N/A

-

01h

DFCTL1

W

11

10

9

8

7

6

5

4

3

2

1

0

B

02h

DFCTL2

W

11

10

9

8

7

6

5

4

3

2

1

0

B

03h

DTK

W

11

10

9

8

7

6

5

4

3

2

1

0

B

04h

DSL1

W

11

10

9

8

7

6

5

4

3

2

1 *

0 *

B

05h

DSL2

W

11

10

9

8

7

6

5

4

3

2

1 *

0 *

B

06h

DSA1

W

11

-

B

07h

DSA2

W

11

-

B

08h

DSP

W

11

10

9

8

7

6

5

4

3

2

1

0

B

09h

DLD

W

11

10

9

8

7

6

5

4

3

2

1

0

B

0Ah

N/A

-

0Bh

N/A

-

Default : 0

* : fixed at 0

** : refer to P.15 about reset

- : not affected even when data is written

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