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X9271TBI-2.7 Datasheet(PDF) 5 Page - Xicor Inc. |
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X9271TBI-2.7 Datasheet(HTML) 5 Page - Xicor Inc. |
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5 / 23 page  X9271 Characteristics subject to change without notice. 5 of 23 REV 1.1.7 2/6/03 www.xicor.com PRINCIPLES OF OPERATION Device Description SERIAL INTERFACE The X9271 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. ARRAY DESCRIPTION The X9271 is comprised of a resistor array (see Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (see Table 1). POWER UP AND DOWN RECOMMENDATIONS. There are no restrictions on the power-up or power- down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate specification is always in effect. Figure 1. Detailed Potentiometer Block Diagram SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 SERIAL BUS INPUT PARALLEL BUS INPUT COUNTER REGISTER INC/DEC LOGIC UP/DN CLK MODIFIED SCK UP/DN RH RL RW 8 8 C O U N T E R D E C O D E IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH WIPER (WCR) BANK_0 Only (DR0) (DR1) (DR2) (DR3) |
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