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ADDR1333C4G9 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers |
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ADDR1333C4G9 Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 16 page 11 ADDR1333C4G9 DDR3-1333(CL9) 240-Pin R-DIMM 4GB(512M x 72-bits) Input DC & AC Logic Level for single-ended signals: Parameter Symbol Min Max Unit Note DC Input logic high voltage VIH (DC) VREF+100 VDD mV 1 DC Input logic low voltage VIL (DC) VSS VREF-100 mV 1 AC input logic high VIH(AC) VREF + 175 - mV 1,2 AC input logic low VIL(AC) - VREF – 175 mV 1,2 Note: 1. For DQ and DM, VREF = VREFDQ . For input only pins except RESET, or VREF = VREFCA. 2. See "Overshoot and Undershoot specifications" on component datasheet Input AC Logic Level for single-ended signals: Parameter Symbol Min Max Unit Note Differential input high VIHdiff +0.2 Note 3 V 1 Differential input low VILdiff Note 3 -0.2 V 1 Differential input high AC VIHdiff(AC) 2 (VIH(ac)-Vref) Note 3 V 2 Differential input low AC VILdiff (AC) Note 3 2 x (Vref - VIL(ac)) V 2 Notes: 1. Used to define a differential signal slew-rate. 2. For CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however they single-ended signals CK, /CK, DQS, /DQS, DQSL, /DQSL, DQSU, /DQSU need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot on Component Datasheet. |
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