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STM32F439VG Datasheet(PDF) 41 Page - STMicroelectronics

Part # STM32F439VG
Description  ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera&LCD-TFT
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F439VG Datasheet(HTML) 41 Page - STMicroelectronics

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DocID024244 Rev 10
41/240
STM32F437xx and STM32F439xx
Functional overview
43
3.35
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
3.36
Cryptographic acceleration
The devices embed a cryptographic accelerator. This cryptographic accelerator provides a
set of hardware acceleration for the advanced cryptographic algorithms usually needed to
provide confidentiality, authentication, data integrity and non repudiation when exchanging
messages with a peer.
These algorithms consists of:
Encryption/Decryption
DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter
mode) chaining algorithms, 128, 192 or 256-bit key
Universal hash
SHA-1 and SHA-2 (secure hash algorithms)
–MD5
–HMAC
The cryptographic accelerator supports DMA request generation.
3.37
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.38
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.


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