BD37521FS

9/27

TSZ02201-0C2C0E100460-1-2

© 2015 ROHM Co., Ltd. All rights reserved.

www.rohm.com

TSZ22111・15・001

16.Dec.2015 Rev.001

Timing Chart

Control Signal Specification

(1) Electrical Specifications and Timing for Bus Lines and I/O Stages

Parameter

Symbol

Unit

Min

Max

1

SCL clock frequency

0

400

kHz

2

Bus free time between a STOP and START condition

1.3

－

μs

3

Hold time (repeated) START condition. After this period,

the first clock pulse is generated

0.6

－

μs

4

LOW period of the SCL clock

1.3

－

μs

5

HIGH period of the SCL clock

0.6

－

μs

6

Set-up time for a repeated START condition

0.6

－

μs

7

Data hold time:

－

μs

8

Data set-up time

120

－

ns

9

Set-up time for STOP condition

0.6

－

μs

All values referred to VIH Min and VIL Max Levels (see Table 2).

(Note) The device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH Min of the SCL signal) in order to bridge the

undefined region of the falling edge of SCL.

Parameter

Symbol

Fast-mode devices

Unit

Min

Max

10

LOW level input voltage:

-0.3

+1

V

11

HIGH level input voltage:

2.3

5

V

12

Pulse width of spikes which must be suppressed by the input filter.

0

50

ns

13

LOW level output voltage: at 3mA sink current

0

0.4

V

14

Input current each I/O pin with an input voltage between 0.4V and

4.5V.

-10

+10

μA

(1)

SDA

S

SCL

P

tHD;STA

Sr

P

SCL clock frequency: 250kHz

SCL

SDA

:2µs

:1µs

:1µs

:2µs

:4µs

:3µs

:1µs