Detailed Description

Converter Operation

The MAX1284/MAX1285 use an input T/H and succes-

sive-approximation register (SAR) circuitry to convert

an analog input signal to a digital 12-bit output. Figure

3 shows the MAX1284/MAX1285 in its simplest configu-

ration. The internal reference is trimmed to +2.5V. The

serial interface requires only three digital lines (SCLK,

CS, and DOUT) and provides an easy interface to

microprocessors (µPs).

The MAX1284/MAX1285 have two modes: normal and

shutdown. Pulling SHDN low shuts the device down and

reduces supply current to below 2µA (typ), while pulling

SHDN high puts the device into operational mode. Pulling

CS low initiates a conversion that is driven by SCLK. The

conversion result is available at DOUT in unipolar serial

format. The serial data stream consists of three zeros,

followed by the data bits (MSB first). All transitions on

DOUT occur 20ns after the rising edge of SCLK. Figures

8 and 9 show the interface timing information.

Analog Input

Figure 4 illustrates the sampling architecture of the

ADC’s comparator. The full-scale input voltage is set by

Track/Hold

In track mode, the analog signal is acquired and stored

in the internal hold capacitor. In hold mode, the T/H

switch opens and maintains a constant input to the

ADC’s SAR section.

During acquisition, the analog input (AIN) charges

interval. At this instant, the T/H switches the input side

resents a sample of the input, unbalancing node ZERO

at the comparator’s input.

In hold mode, the capacitive digital-to-analog converter

(DAC) adjusts during the remainder of the conversion

cycle to restore node ZERO to 0 within the limits of 12-

bit resolution. This action is equivalent to transferring a

DAC, which in turn forms a digital representation of the

analog input signal. At the conversion’s end, the input

400ksps/300ksps, Single-Supply, Low-Power,

Serial 12-Bit ADCs with Internal Reference

8

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DOUT

DOUT

6k

Ω

DGND

6k

Ω

DGND

Figure 1. Load Circuits for DOUT Enable Time

DOUT

DOUT

6k

Ω

DGND

6k

Ω

DGND

Figure 2. Load Circuits for DOUT Disable Time