SRAM

AS5C512K8

AS5C512K8

Rev. 7.5 01/13

Micross Components reserves the right to change products or specifications without notice.

5

Inputpulselevels...............................................Vssto3.0V

Inputriseandfalltimes..................................................3ns

Inputtimingreferencelevels........................................1.5V

Outputreferencelevels..................................................1.5V

Outputload.................................................SeeFigures1

and2

NOTES

1. AllvoltagesreferencedtoV

2. -2Vforpulsewidth<20ns

3. I

4. Thisparameterisguaranteedbutnottested.

5. Testconditionsasspecifiedwiththeoutputloading

asshowninFig.1unlessotherwisenoted.

arespecifiedwithCL=5pFasinFig.2.Transitionis

measured±200mVfromsteadystatevoltage.

7. Atanygiventemperatureandvoltagecondition,

t

t

LZWE.

8. WE\isHIGHforREADcycle.

9. Deviceiscontinuouslyselected.Chipenablesand

outputenablesareheldintheiractivestate.

10. Addressvalidpriorto,orcoincidentwith,latest

occurringchipenable.

12. Chipenableandwriteenablecaninitiateand

terminateaWRITEcycle.

13. Outputenable(OE\)isinactive(HIGH).

14. Outputenable(OE\)isactive(LOW).

15.ASIdoesnotwarrantfunctionalitynorreliabilityof

anyproductinwhichthejunctiontemperature

exceeds150°C.Careshouldbetakentolimitpowerto

acceptablelevels.

Fig. 1 Output Load

Equivalent

Fig. 2 Output Load

Equivalent

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

AC TEST CONDITIONS

DESCRIPTION

SYM

MIN MAX UNITS NOTES

Vcc for Retention Data

2V

Data Retention Current

Vcc = 2.0V

2

mA

Chip Deselect to Data

0

ns

4

Operation Recovery Time

10

ms

4, 11

CONDITIONS

SRAM

SRAM

SRAM

SRAM

SRAM

AS5C512K8

AS5C512K8

Rev. 7.0 05/08

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

Austin Semiconductor, Inc.

167 ohms

167 ohms

1.73V

1.73V

C=5pF

C=30pF

Q

Q

Input pulse levels ...................................................... Vss to 3.0V

Input rise and fall times ......................................................... 3ns

Input timing reference levels ............................................... 1.5V

Output reference levels ........................................................ 1.5V

Output load ................................................. See Figures 1 and 2

NOTES

1.

All voltages referenced to V

2.

-2V for pulse width < 20ns

3.

I

4.

This parameter is guaranteed but not tested.

5.

Test conditions as specified with the output loading

as shown in Fig. 1 unless otherwise noted.

6.

t

are specified with CL = 5pF as in Fig. 2. Transition is

measured ±200mV from steady state voltage.

7.

At any given temperature and voltage condition,

t

t

LZWE.

8.

WE\ is HIGH for READ cycle.

9.

Device is continuously selected. Chip enables and

output enables are held in their active state.

10. Address valid prior to, or coincident with, latest

occurring chip enable.

12. Chip enable and write enable can initiate and

terminate a WRITE cycle.

13. Output enable (OE\) is inactive (HIGH).

14. Output enable (OE\) is active (LOW).

15. ASI does not warrant functionality nor reliability of

any product in which the junction temperature

exceeds 150°C. Care should be taken to limit power to

acceptable levels.

Fig. 1 Output Load

Equivalent

Fig. 2 Output Load

Equivalent

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

AC TEST CONDITIONS

DESCRIPTION

SYM

MIN

MAX

UNITS

NOTES

Vcc for Retention Data

2V

Data Retention Current

Vcc = 2.0V

800

uA

Chip Deselect to Data

0

ns

4

Operation Recovery Time

10

ms

4, 11

CONDITIONS