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MC74HCT374A Datasheet(PDF) 1 Page - ON Semiconductor |
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MC74HCT374A Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 12 1 Publication Order Number: MC74HCT374A/D MC74HCT374A Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT374A may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. The HCT374A is identical in pinout to the LS374. Data meeting the setup and hold time is clocked to the outputs with the rising edge of Clock. The Output Enable does not affect the state of the flip−flops, but when Output Enable is high, the outputs are forced to the high−impedance state. Thus, data may be stored even when the outputs are not enabled. The HCT374A is identical in function to the HCT574A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT534A, which has inverting outputs. Features • Output Drive Capability: 15 LSTTL Loads • TTL/NMOS−Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 mA • In Compliance With the JEDEC Standard No. 7.0 A Requirements • Chip Complexity: 276 FETs or 69 Equivalent Gates • Improvements over HCT374 ♦ Improved Propagation Delays ♦ 50% Lower Quiescent Power ♦ Improved Input Noise and Latchup Immunity • These Devices are Pb−Free and are RoHS Compliant LOGIC DIAGRAM DATA INPUTS D0 11 CLOCK D1 D2 D3 D4 D5 D6 D7 18 17 14 13 8 7 4 3 1 OUTPUT ENABLE 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 16 15 12 9 6 5 2 PIN 20 = VCC PIN 10 = GND NONINVERTING OUTPUTS http://onsemi.com MARKING DIAGRAMS HCT 374A ALYW G G See detailed ordering and shipping information on page 5 of this data sheet. ORDERING INFORMATION 20 1 HCT374A AWLYYWWG 20 1 SOIC−20 TSSOP−20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) SOIC−20 DW SUFFIX CASE 751D TSSOP−20 DT SUFFIX CASE 948E PIN ASSIGNMENT Q2 D1 D0 Q0 OUTPUT ENABLE GND Q3 D3 D2 Q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 Q6 D6 D7 Q7 VCC CLOCK Q4 D4 D5 Q5 FUNCTION TABLE Inputs Output Output Enable Clock D Q LH H LL L L L,H, X No Change HX X Z X = don’t care Z = high impedance |
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