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MC74HCT273ADTR2G Datasheet(PDF) 3 Page - ON Semiconductor

Part # MC74HCT273ADTR2G
Description  Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74HCT273ADTR2G Datasheet(HTML) 3 Page - ON Semiconductor

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MC74HCT273A
http://onsemi.com
3
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Fig.
Guaranteed Limit
Unit
−55 to
25
_C
≤ 85_C
≤ 125_C
fmax
Maximum Clock Frequency (50% Duty Cycle)
2, 5
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
2, 5
25
28
35
ns
tPHL
Maximum Propagation Delay, Reset to Q
25
28
35
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
2, 5
18
20
22
ns
CPD
Power Dissipation Capacitance (Per Gate)*
Typical @ 25
°C, VCC = 5.0 V
pF
30
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
TIMING REQUIREMENTS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Fig.
Guaranteed Limit
Unit
–55 to 25
_C
≤ 85_C
≤ 125_C
Min
Max
Min
Max
Min
Max
tsu
Minimum Setup Time, Data to Clock
10
12
15
ns
th
Minimum Hold Time, Clock to Data
3.0
3.0
3.0
ns
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
2
12
15
18
ns
tw
Minimum Pulse Width, Set or Reset
12
15
18
ns
tr, tf
Maximum Input Rise and Fall Times
2
500
500
500
ns
Figure 2.
CLOCK
Q
tr
tf
3.0 V
GND
2.7 V
1.3 V
0.3 V
90%
1.3 V
10%
tPLH
tPHL
tTLH
tTHL
Figure 3.
tw
1/fmax
RESET
Q
CLOCK
tw
1.3 V
1.3 V
1.3 V
3.0 V
GND
3.0 V
GND
tPHL
trec
SWITCHING WAVEFORMS


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