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TH71221ELQBAA-000TU Datasheet(PDF) 5 Page - Melexis Microelectronic Systems |
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TH71221ELQBAA-000TU Datasheet(HTML) 5 Page - Melexis Microelectronic Systems |
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5 / 44 page  TH71221 27 to 930MHz FSK/FM/ASK Transceiver 39010 071221 Page 5 of 44 Data Sheet Rev. 009 Nov/15 1.4 Block Diagram Fig. 1: TH71221 block diagram 1.5 User Mode Features The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to Stand- alone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC in order to set the desired frequency of operation. There are 4 pre-defined frequency settings: 315MHz, 433.92MHz, 868.3MHz and 915MHz. The logic level at pin FS0/SDEN must not be changed after power up in order to remain in fixed-frequency mode. After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode (PUM). In this mode, the user can set any PLL frequency or mode of operation by the SCI. In SUM pins FS0/SDEN and FS1/LD are used to set the desired frequency, while in PUM pin FS0/SDEN is part of the 3-wire serial control interface (SCI) and pin FS1/LD is the look detector output signal of the PLL synthesizer. A mode control logic allows several operating modes. In addition to standby, transmit and receive mode, two idle modes can be selected to run either the reference oscillator only or the whole PLL synthesizer. The PLL settings for the PLL idle mode are taken over from the last operating mode which can be either receive or transmit mode. The different operating modes can be set in SUM and PUM as well. In SUM the user can program the trans- ceiver via control pins RE/SCLK and TE/SDTA. In PUM the register bits OPMODE are used to select the modes of operation while pins RE/SCLK and TE/SDTA are part of the SCI. IN_LNA LNA IF MIX 26 29 28 30 32 31 1 27 IFA 2 7 1.5pF IN_DEM 3 MIX Demodulator FSK OUT_DTA OA2 bias OUT_DEM SW1 SW2 6 OA1 8 INT1 5 INT2/PDO 4 200k VEE_PLL OUT_PA FSK ASK LO 25 PS_PA 24 11 19 9 17 16 15 13 12 RO RO R counter N counter RO 10 Control Logic SCI PKDET VCO PA VCC_PLL 20 TNK_LO 23 22 LF 21 18 14 |
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