Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. E

11/26/03

IS62C1024L

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

DESCRIPTION

The

CMOS static RAM. It is fabricated using

CMOS technology. This highly reliable process coupled

with innovative circuit design techniques, yields higher

performance and low power consumption devices.

When

CE1 is HIGH or CE2 is LOW (deselected), the

device assumes a standby mode at which the power

dissipation can be reduced by using CMOS input levels.

Easy memory expansion is provided by using two Chip

Enable inputs,

CE1 and CE2. The active LOW Write

Enable (

WE) controls both writing and reading of the

memory.

The IS62C1024L is available in 32-pin plastic SOP and

TSOP (type 1) packages.

FUNCTIONAL BLOCK DIAGRAM

128K x 8 LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 35, 70 ns

• Low active power: 450 mW (typical)

• Low standby power: 150 µW (typical) CMOS

standby

• Output Enable (

OE) and two Chip Enable

(

CE1 and CE2) inputs for ease in applications

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single 5V (±10%) power supply

A0-A16

CE1

OE

WE

128K x 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VDD

I/O

DATA

CIRCUIT

I/O0-I/O7

CE2

DECEMBER 2003