1

Rev. A

02/21/03

IS61LV25616AL

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• High-speed access time:

— 10, 12 ns

• CMOS low power operation

• Low stand-by power:

• TTL compatible interface levels

• Single 3.3V power supply

• Fully static operation: no clock or refresh

required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

256K x 16 HIGH SPEED ASYNCHRONOUS

CMOS STATIC RAM WITH 3.3V SUPPLY

DESCRIPTION

The

static RAM organized as 262,144 words by 16 bits. It is

fabricated using

ogy. This highly reliable process coupled with innovative

circuit design techniques, yields high-performance and low

power consumption devices.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs,

CE and OE. The active LOW

Write Enable (

WE) controls both writing and reading of the

memory. A data byte allows Upper Byte (

UB) and Lower

Byte (

LB) access.

The IS61LV25616AL is packaged in the JEDEC standard

44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and

48-pin Mini BGA (8mm x 10mm).

FUNCTIONAL BLOCK DIAGRAM

A0-A17

CE

OE

WE

256K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VDD

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

FEBRUARY 2003