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TPS40422RHAR Datasheet(PDF) 3 Page - Texas Instruments |
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TPS40422RHAR Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 71 page  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 RT FB1 COMP1 CNTL1 CNTL2 AGND COMP2 FB2 ADDR1 ADDR0 TPS40422 BOOT1 HDRV1 SW1 LDRV1 PGND BP6 BPEXT LDRV2 SW2 HDRV2 3 TPS40422 www.ti.com SLUSAQ4E – OCTOBER 2011 – REVISED SEPTEMBER 2016 Product Folder Links: TPS40422 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated 5 Description (continued) Using the PMBus protocol, the device margining function, reference voltage, fault limit, UVLO threshold, soft-start time, turn-on delay, and turn-off delay can be programmed. In addition, an accurate measurement system is implemented to monitor the output voltages, currents and temperatures for each channel. 6 Pin Configuration and Functions RHA Packages 40-Pin VQFN Top View Pin Functions PIN NO. I/O DESCRIPTION ADDR0 10 I Low-order address pin for PMBus address configuration. One of eight resistor values must be connected from this pin to AGND to select the low-order octal digit in the PMBus address. ADDR1 9 I High-order address pin for PMBus address configuration. One of eight resistor values must be connected from this pin to AGND to select the high-order octal digit in the PMBus address. AGND 6 — Low-noise ground connection to the controller. Connections should be arranged so that power level currents do not flow through the AGND path. BOOT1 30 I Bootstrapped supply for the high-side FET driver for channel 1 (CH1). Connect a capacitor (100 nF typical) from BOOT1 to SW1 pin. BOOT2 20 I Bootstrapped supply for the high-side FET driver for channel 2 (CH2). Connect a capacitor (100 nF typical) from BOOT2 to SW2 pin. BP3 32 O Output bypass for the internal 3.3-V regulator. Connect a 100 nF or larger capacitor from this pin to AGND. The maximum suggested capacitor value is 10 µF. BP6 25 O Output bypass for the internal 6.5-V regulator. Connect a low ESR, 1 µF or larger ceramic capacitor from this pin to PGND. The maximum suggested capacitor value is 10 µF. BPEXT 24 I External voltage input for BP6 switchover function. If the BPEXT function is not used, connect this pin to PGND via a 10-kΩ resistor. Otherwise connect a 100-nF or larger capacitor from this pin to PGND. The maximum suggested capacitor value is 10 µF. CLK 12 I Clock input for the PMBus interface. Pull up to 3.3 V with a resistor. CNTL1 4 I Logic level input which controls startup and shutdown of CH1, determined by PMBus options. When floating, the pin is pulled up to BP6 by an internal 6-µA current source. |
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