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ADF4360-4BCP Datasheet(PDF) 5 Page - Analog Devices |
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ADF4360-4BCP Datasheet(HTML) 5 Page - Analog Devices |
5 / 20 page PRELIMINARY TECHNICAL DATA REV. PrA 07/03 –5– ADF4360-2 PIN DESCRIPTION Mnemonic Function AV DD Analog Power Supply. This may range from 3.0V to 3.6V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. DV DD Digital Power Supply. This may range from 3.0V to 3.6V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. VVCO Power supply for the VCO. This may range from 3.0V to 3.6V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VVCO must be the same value as AVDD. RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer. The nominal voltage potential at the RSET pin is 0.6V. The relationship between ICP and RSET is So, with RSET = 4.7k Ω, I CPmax = 2.5mA. MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to be accessed externally. C P Charge Pump Output. When enabled this provides ±ICP to the external loop filter, which in turn drives the internal VCO. V TUNE Control input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT voltage. C C Internal compensation node. This pin must be decoupled to ground with a 10nF capacitor. C N Internal compensation node. This pin must be decoupled to VVCO with a 10uF capacitor. RFOUTA VCO output. The output level is programmable from -6dBm to -13dBm. See Page 18 for a description of various output stages. RF OUTB VCO complementary output. The output level is programmable from -6dBm to -13dBm. See Page 18 for a description of various output stages. CPGND Charge Pump Ground. This is the ground return path for the charge pump. DGND Digital Ground. AGND Analog Ground. This is the ground return path of the prescaler & VCO. L E Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the relevant latch is selected using the control bits. DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. C L K Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. C E Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three state mode. Taking the pin high will power up the device depending on the status of the power-down bits. REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100k Ω. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac coupled. ICPmax = RSET 11.75 |
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