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K9K1208U0M-YCB0 Datasheet(PDF) 2 Page - Samsung semiconductor

Part # K9K1208U0M-YCB0
Description  64M x 8 Bit NAND Flash Memory
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

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K9K1208U0M-YCB0, K9K1208U0M-YIB0
FLASH MEMORY
2
64M x 8 Bit NAND Flash Memory
The K9K1208U0M are a 64M(67,108,864)x8bit NAND Flash
Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell
provides the most cost-effective solution for the solid state
mass storage market. A program operation programs the 528-
byte page in typically 200
µs and an erase operation can be per-
formed in typically 2ms on a 16K-byte block. Data in the page
can be read out at 60ns cycle time per byte. The I/O pins serve
as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verify and margining of data. Even the
write-intensive
systems
can
take
advantage
of
the
K9K1208U0M
′s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. The K9K1208U0M-YCB0/YIB0 is an
optimum solution for large nonvolatile storage applications such
as solid state file storage and other portable applications requir-
ing non-volatility.
GENERAL DESCRIPTION
FEATURES
• Voltage Supply : 2.7V~3.6V
• Organization
- Memory Cell Array : (64M + 2,048K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• 528-Byte Page Read Operation
- Random Access : 10
µs(Max.)
- Serial Page Access : 60ns(Min.)
• Fast Write Cycle Time
- Program time : 200
µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Package :
- K9K1208U0M-YCB0/YIB0 :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
PIN CONFIGURATION
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
48-pin TSOP1
Standard Type
12mm x 20mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Pin Name
Pin Function
I/O0 ~ I/O7
Data Input/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
GND
GND input for enabling spare area
R/B
Ready/Busy output
VCC
Power
VSS
Ground
N.C
No Connection
PIN DESCRIPTION


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