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TAS5780M Datasheet(PDF) 10 Page - Texas Instruments |
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TAS5780M Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 204 page  10 TAS5780M SLASEG7 – DECEMBER 2016 www.ti.com Product Folder Links: TAS5780M Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK,RESET, SCL, SCLK, SDA, SDIN, and SPK_MUTE. (2) A unit of fS indicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the TAS5780M device. 7.5 Electrical Characteristics Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5780MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL I/O |IIH|1 Input logic high current level for DVDD referenced digital input pins(1) VIN(DigIn) = VDVDD 10 µA |IIL|1 Input logic low current level for DVDD referenced digital input pins(1) VIN(DigIn) = 0 V –10 µA VIH1 Input logic high threshold for DVDD referenced digital inputs(1) 70% VDVDD VIL1 Input logic low threshold for DVDD referenced digital inputs(1) 30% VDVDD VOH(DigOut) Output logic high voltage level(1) IOH = 4 mA 80% VDVDD VOL(DigOut) Output logic low voltage level(1) IOH = –4 mA 22% VDVDD VOL(SPK_FAULT) Output logic low voltage level for SPK_FAULT With 100-kΩ pullup resistor 0.8 V GVDD_REG GVDD regulator voltage 7 V I2C CONTROL PORT CL(I2C) Allowable load capacitance for each I2C Line 400 pF fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz VNH Noise margin at High level for each connected device (including hysteresis) 0.2 × VDD V MCLK AND PLL SPECIFICATIONS DMCLK Allowable MCLK duty cycle 40% 60% fMCLK Supported MCLK frequencies Up to 50 MHz 128 512 fS (2) fPLL PLL input frequency Clock divider uses fractional divide D > 0, P = 1 6.7 20 MHz Clock divider uses integer divide D = 0, P = 1 1 20 SERIAL AUDIO PORT tDLY Required LRCK/FS to SCLK rising edge delay 5 ns DSCLK Allowable SCLK duty cycle 40% 60% fS Supported input sample rates 8 96 kHz fSCLK Supported SCLK frequencies 32 64 fS (2) fSCLK SCLK frequency Either master mode or slave mode 24.576 MHz SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS) AV(SPK_AMP) Speaker amplifier gain SPK_GAIN/FREQ voltage < 3 V, see Adjustable Amplifier Gain and Switching Frequency Selection 20 dBV SPK_GAIN/FREQ voltage > 3.3 V, see Adjustable Amplifier Gain and Switching Frequency Selection 26 ΔAV(SPK_AMP) Typical variation of speaker amplifier gain ±1 dBV |
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