HIGH-PER.ORMANCE PRODUCTS

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Revision 1/.ebruary 13, 2001

SK10/100E016

8-Bit Synchronous

Binary Up Counter

Description

.eatures

.unctional Block Diagram

The SK10/100E016 is a high-speed synchronous,

presettable, cascadable 8-bit binary counter.

The counter features internal feedback of TC*, gated by

the TCLD (terminal count load) pin. When TCLD is LOW

(or left open, in which case it is pulled LOW by the internal

pull-downs), the TC* feedback is disabled, and counting

proceeds continuously, with TC* going LOW to indicate

an all-one state. When TCLD is HIGH, the TC* feedback

causes the counter to automatically reload upon TC* =

LOW, thus functioning as a programmable counter. The

Qn outputs do not need to be terminated for the count

function to operate properly.

To minimize noise and

power, unused Q outputs should be left unterminated.

•

700 MHz Min Count Frequency

•

1000 ps CLK to Q, TC*

•

Internal TC* Feedback (Gated)

•

8-Bit

•

Fully Synchronous Counting and TC* Generation

•

Asynchronous Master Reset

•

Internal 75 k

Ω Input Pulldown Resistors

•

•

Fully Compatible with MC10/100E016

•

Available in 28-Pin PLCC Package

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ESD Protection of >4000V

CE*

Q0*

BIT 1

BIT 0

BIT 7

CE*

Q0*

Q1*

Q4*

Q5*

Q6*

Q2*

Q3*

P1

P7

Q0

Q1

Q7

5

TC*

PE

TCLD

CE*

PO

MR

CLK

MASTER

SLAVE

QOM*

QOM

BITS 2-6

Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation

delays as many gate functions are achieved internally without incurring a full gate delay.

8 Bit Binary Counter - Logic Counter