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IDT72V3676 Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72V3676 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 39 page 9 COMMERCIALTEMPERATURERANGE IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE IDT72V3656L10(1) IDT72V3656L15 IDT72V3666L10(1) IDT72V3666L15 IDT72V3676L10(1) IDT72V3676L15 Symbol Parameter Min. Max. Min. Max. Unit fS Clock Frequency, CLKA, CLKB, or CLKC — 100 — 66.7 MHz tCLK Clock Cycle Time, CLKA, CLKB, or CLKC 10 — 15 — ns tCLKH Pulse Duration, CLKA, CLKB, or CLKC HIGH 4.5 — 6 — ns tCLKL Pulse Duration, CLKA, CLKB, OR CLKC LOW 4.5 — 6 — ns tDS Setup Time, A0-A35 before CLKA ↑ and C0-C17 before CLKC↑ 3— 4— ns tENS1 Setup Time, CSA and W/RA before CLKA ↑; CSB 4 — 4.5 — ns before CLKB ↑ tENS2 Setup Time, ENA, and MBA before CLKA ↑; RENB 3 — 4.5 — ns and MBB before CLKB ↑; WENC and MBC before CLKC↑ tRSTS Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 5— 5— ns LOW before CLKA ↑orCLKB↑(2) tFSS Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH 7.5 — 8.5 — ns tBES Setup Time, BE/ FWFT before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns tSDS Setup Time, FS0/SD before CLKA ↑ 3— 4— ns tSENS Setup Time, FS1/ SEN before CLKA ↑ 3— 4— ns tFWS Setup Time, BE/ FWFT before CLKA ↑ 0— 0— ns tRTMS Setup Time, RTM before RT1; RTM before RT2 5— 5— ns tDH Hold Time, A0-A35 after CLKA ↑ and C0-C17 after CLKC↑ 0.5 — 1 — ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA ↑; CSB, 0.5 — 1 — ns RENB, and MBB after CLKB ↑; WENC and MBC after CLKC↑ tRSTH Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 4— 4— ns LOW after CLKA ↑orCLKB↑(2) tFSH Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH 2 — 2 — ns tBEH Hold Time, BE/ FWFT after MRS1 and MRS2 HIGH 2 — 2 — ns tSDH Hold Time, FS0/SD after CLKA ↑ 0.5 — 1 — ns tSENH Hold Time, FS1/ SEN HIGH after CLKA ↑ 0.5 — 1 — ns tSPH Hold Time, FS1/ SEN HIGH after MRS1 and MRS2 HIGH 2 — 2 — ns tRTMH Hold Time, RTM after RT1; RTM after RT2 5— 5— ns tSKEW1(3) Skew Time, between CLKA ↑ and CLKB↑ for EFB/ORB and 5 — 7.5 — ns FFA/IRA; between CLKA ↑ and CLKC↑ for EFA/ORA and FFC/IRC tSKEW2(3,4) Skew Time, between CLKA ↑ andCLKB↑ forAEBandAFA;12 — 12 — ns between CLKA ↑ and CLKC↑ for AEA and AFC NOTES: 1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle. 4. Design simulated, not tested. (For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0 °C to +70°C; JEDEC JESD8-A compliant) |
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