9

COMMERCIALTEMPERATURERANGE

WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

IDT72V3656L15

IDT72V3666L15

IDT72V3676L15

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Clock Frequency, CLKA, CLKB, or CLKC

—

100

—

66.7

MHz

Clock Cycle Time, CLKA, CLKB, or CLKC

10

—

15

—

ns

Pulse Duration, CLKA, CLKB, or CLKC HIGH

4.5

—

6

—

ns

Pulse Duration, CLKA, CLKB, OR CLKC LOW

4.5

—

6

—

ns

Setup Time, A0-A35 before CLKA

↑ and C0-C17 before CLKC↑

3—

4—

ns

Setup Time,

CSA and W/RA before CLKA

↑; CSB

4

—

4.5

—

ns

before CLKB

↑

Setup Time, ENA, and MBA before CLKA

↑; RENB

3

—

4.5

—

ns

and MBB before CLKB

↑; WENC and MBC before CLKC↑

Setup Time,

MRS1, MRS2, PRS1, PRS2, RT1 or RT2

5—

5—

ns

LOW before CLKA

Setup Time, FS0, FS1, FS2 before

MRS1 and MRS2 HIGH

7.5

—

8.5

—

ns

Setup Time, BE/

FWFT before MRS1 and MRS2 HIGH

7.5

—

7.5

—

ns

Setup Time, FS0/SD before CLKA

↑

3—

4—

ns

Setup Time, FS1/

SEN before CLKA

↑

3—

4—

ns

Setup Time, BE/

FWFT before CLKA

↑

0—

0—

ns

Setup Time, RTM before RT1; RTM before RT2

5—

5—

ns

Hold Time, A0-A35 after CLKA

↑ and C0-C17 after CLKC↑

0.5

—

1

—

ns

Hold Time,

CSA, W/RA, ENA, and MBA after CLKA

↑; CSB,

0.5

—

1

—

ns

RENB, and MBB after CLKB

↑; WENC and MBC after CLKC↑

Hold Time,

MRS1, MRS2, PRS1, PRS2, RT1 or RT2

4—

4—

ns

LOW after CLKA

Hold Time, FS0, FS1, FS2 after

MRS1 and MRS2 HIGH

2

—

2

—

ns

Hold Time, BE/

FWFT after MRS1 and MRS2 HIGH

2

—

2

—

ns

Hold Time, FS0/SD after CLKA

↑

0.5

—

1

—

ns

Hold Time, FS1/

SEN HIGH after CLKA

↑

0.5

—

1

—

ns

Hold Time, FS1/

SEN HIGH after MRS1 and MRS2 HIGH

2

—

2

—

ns

Hold Time, RTM after RT1; RTM after RT2

5—

5—

ns

Skew Time, between CLKA

↑ and CLKB↑ for EFB/ORB and

5

—

7.5

—

ns

FFA/IRA; between CLKA

↑ and CLKC↑ for EFA/ORA and

FFC/IRC

Skew Time, between CLKA

↑ andCLKB↑ forAEBandAFA;12

—

12

—

ns

between CLKA

↑ and CLKC↑ for AEA and AFC

NOTES:

1. For 10ns speed grade: Vcc = 3.3V

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.

4. Design simulated, not tested.

°C to +70°C; JEDEC JESD8-A compliant)