6.42

IDT71V30S/L

High-Speed 1K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

5

AC Test Conditions

Data Retention Waveform

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. 'X' in part number indicates power rating (S or L).

4. Industrial temperature: for specific speeds, packages and power contact your sales office.

Figure 2. Output Test Load

* Including scope and jig.

Figure 1. AC Output Test Load

AC Electrical Characteristics Over the

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

1.5V

Figures 1 and 2

3741 tbl 08

CE

3.0V

3.0V

DATA RETENTION MODE

≥ 2.0V

3741 drw 04

,

590

Ω

30pF

435

Ω

590

Ω

435

Ω

5pF

3741 drw 05

3.3V

3.3V

BUSY

INT

71V30X25

Com'l Only

71V30X35

Com'l & Ind

71V30X55

Com'l Only

Unit

Symbol

Parameter

Min.Max.Min.Max.Min.Max.

READ CYCLE

Read Cycle Time

25

____

35

____

55

____

ns

Address Access Time

____

25

____

35

____

55

ns

Chip Enable Access Time

____

25

____

35

____

55

ns

Output Enable Access Time

____

12

____

20

____

25

ns

Output Hold from Address Change

3

____

3

____

3

____

ns

0

____

0

____

0

____

ns

____

12

____

15

____

30

ns

0

____

0

____

0

____

ns

____

50

____

50

____

50

ns

3741 tbl 09