 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
70V639S15BCGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
70V639S15BCGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
|
|
1 / 24 page  ©2015 Integrated Device Technology, Inc. JUNE 2015 DSC-5621/7 1 CE0R R/ WR CE1R LBR UBR 128K x 18 MEMORY ARRAY Address Decoder A16R A0R Address Decoder CE0L R/ WL CE1L LBL UBL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R B E 0 L B E 1 L B E 1 R B E 0 R I/O0L-I/O17L I/O0R -I/O17R Din_L ADDR_L Din_R ADDR_R OER OEL ARBITRATION INTERRUPT SEMAPHORE LOGIC SEML INTL BUSYL M/ S R/ WL OEL R/ WR OER BUSYR SEMR INTR CE0L CE1L CE0R CE1R TMS TCK TRST TDI TDO JTAG 5621 drw 01 A16L A0L Functional Block Diagram ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ ◆ ◆ ◆ ◆ Supports JTAG features compliant to IEEE 1149.1 – Due to limited pin count, JTAG is not supported on the 128-pin TQFP package. ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, single 3.3V (±150mV) power supply for core ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port ◆ ◆ ◆ ◆ ◆ Available in a 128-pin Thin Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information Features ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12/15ns (max.) ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without external logic ◆ ◆ ◆ ◆ ◆ IDT70V639 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM IDT70V639S NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). |
Similar Part No. - 70V639S15BCGI8 |
|
Similar Description - 70V639S15BCGI8 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
