6.42

IDT70V37L

High-Speed 3.3V 32K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

6

Timing of Power-Up Power-Down

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.

has no relation to valid output data.

6. Refer toTruth Table I - Chip Enable.

4851 drw 06

50%

50%

.

R/

W

CE

ADDR

OE

UB, LB

4851 drw 05

(4)

(4)

(4)

(4)

(1)

(2)

(3,4)

VALID DATA

(4)

(6)

AC Test Conditions

Figure 1. AC Output Load

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

1.5V

Figures 1 and 2

4851 tbl 11

4851 drw 04

590

Ω

30pF

435

Ω

3.3V

BUSY

INT

590

Ω

5pF*

435

Ω

3.3V

4851 drw 03

Figure 2. Output Test Load

* Including scope and jig.