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70V18L15PFG Datasheet(PDF) 1 Page - Integrated Device Technology

Part # 70V18L15PFG
Description  HIGH-SPEED 3.3V 64K x 9 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

70V18L15PFG Datasheet(HTML) 1 Page - Integrated Device Technology

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©2015 Integrated Device Technology, Inc.
1
MARCH 2015
DSC-4854/6
I/O
Control
Address
Decoder
64Kx9
MEMORY
ARRAY
70V18
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE 0L
OEL
R/
WL
A15L
A0L
I/O 0-8L
SEML
INTL
(2)
BUSYL
(1,2)
R/
W L
CE0L
OE
L
I/O
Control
Address
Decoder
OER
R/
WR
CE0R
A15R
A 0R
I/O 0-8R
SEMR
INT R
(2)
R
BUSY
(1,2)
M/
S
(1)
CE1L
R/
WR
CE0R
OER
CE1R
4854 drw 01
1L
CE
1R
CE
16
16
Functional Block Diagram
IDT70V18 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V18L
Active: 440mW (typ.)
Standby: 660µW (typ.)
Dual chip enables allow for depth expansion without
external logic
Busy and Interrupt Flags
On-chip port arbitration logic
HIGH-SPEED 3.3V
64K x 9 DUAL-PORT
STATIC RAM
IDT70V18L
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).


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