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70V27L25PFG8 Datasheet(PDF) 9 Page - Integrated Device Technology |
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70V27L25PFG8 Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 21 page  Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM 9 Waveform of Read Cycles(5) Timing of Power-Up Power-Down NOTES: 1. Timing depends on which signal is asserted last: CE, OE, LB, or UB. 2. Timing depends on which signal is de-asserted first: CE, OE, LB, or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. 6. Refer to Chip Enable Truth Table. tRC R/ W CE ADDR tAA OE UB, LB 3603 drw 05 (4) tACE (4) tAOE(4) tABE(4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATAOUT BUSYOUT VALID DATA (4) (6) CE 3603 drw 06 tPU ICC ISB tPD 50% 50% (6) , |
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