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70V261S25PFGI Datasheet(PDF) 11 Page - Integrated Device Technology |
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70V261S25PFGI Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 17 page 6.42 IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges 11 Timing Waveform of Write with BUSY Waveform of BUSY Arbitration Controlled by CE Timing(1) NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) 3040 drw 12 R/ W"A" BUSY"B" tWP tWB R/ W"B" tWH (1) (2) 3040 drw 13 ADDR"A" and "B" ADDRESSES MATCH CE"A" CE"B" BUSY"B" tAPS tBAC tBDC (2) 3040 drw 14 ADDR"A" ADDRESS "N" ADDR"B" BUSY"B" tAPS tBAA tBDA (2) MATCHING ADDRESS "N" |
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