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70V261L35PFGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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70V261L35PFGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 17 page  ©2012 Integrated Device Technology, Inc. SEPTEMBER 2012 DSC-3040/11 1 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL BUSYL A13L A0L 3040 drw 01 UBL LBL CEL OEL I/O8L-I/O15L I/O0L-I/O7L CEL OEL R/ WL SEML INTL M/ S R/ WR BUSYR UBR LBR CER OER I/O8R-I/O15R I/O0R-I/O7R A13R A0R R/ WR SEMR INTR CER OER (2) (1,2) (1,2) (2) 14 14 IDT70V261S/L HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 25/35/55ns (max.) – Industrial: 25ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT70V261S Active: 300mW (typ.) Standby: 3.3mW (typ.) – IDT70V261L Active: 300mW (typ.) Standby: 660 µW (typ.) ◆ ◆ ◆ ◆ ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆ ◆ ◆ ◆ IDT70V261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Interrupt Flag ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 3.3V (±0.3V) power supply ◆ ◆ ◆ ◆ ◆ Available in a 100-pin TQFP, Thin Quad Plastic Flatpack ◆ ◆ ◆ ◆ ◆ Industrial temperature range (-40°C to +85°C) is available for selected speed ◆ Green parts available, see ordering information Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. |
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