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71V321S25JGI Datasheet(PDF) 11 Page - Integrated Device Technology |
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71V321S25JGI Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 15 page 6.42 IDT71V321S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 11 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) NOTES: 1. 'X' in part numbers indicates power rating (S or L). 71V321X25 Com'l & Ind 71V321X35 Com'l & Ind 71V321X55 Com'l & Ind Symbol Parameter Min.Max. Min.Max. Min.Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 25 ____ 25 ____ 45 ns tINR Interrupt Reset Time ____ 25 ____ 25 ____ 45 ns 3026 tbl 12 TimingWaveformof InterruptMode(1) SET INT CLEAR INT NOTES:. 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. tINS ADDR"A" INT"B" INTERRUPT ADDRESS tWC tAS R/ W"A" tWR 3026 drw 14 (3) (3) (2) (4) tRC INTERRUPT CLEAR ADDRESS ADDR"B" OE"B" tINR INT"B" 3026 drw 15 tAS(3) (3) (2) , |
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