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70V07L35PFG Datasheet(PDF) 7 Page - Integrated Device Technology |
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70V07L35PFG Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 19 page 7 IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions Figure 1. AC Output Test Load Timing of Power-Up Power-Down NOTES: 1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. 'X' in part number indicates power rating (S or L). AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) CE 2943 drw 07 tPU ICC ISB tPD , Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V Figures 1 and 2 2943 tbl 10 Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig. 2943 drw 06 590 Ω 30pF 435 Ω 3.3V DATAOUT BUSY I NT 590 Ω 5pF* 435 Ω 3.3V DATAOUT 2943 drw 05 70V07X25 Com'l & Ind 70V07X35 Com'l & Ind 70V07X55 Com'l Only Unit Symbol Parameter Min. Max.Min.Max.Min.Max. READ CYCLE tRC Read Cycle Time 25 ____ 35 ____ 55 ____ ns tAA Address Access Time ____ 25 ____ 35 ____ 55 ns tACE Chip Enable Access Time(3) ____ 25 ____ 35 ____ 55 ns tAOE Output Enable Access Time ____ 15 ____ 20 ____ 30 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time(1,2) 3 ____ 3 ____ 3 ____ ns tHZ Output High-Z Time(1,2) ____ 15 ____ 20 ____ 25 ns tPU Chip Enable to Power Up Time(2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time(2) ____ 25 ____ 35 ____ 50 ns tSOP Semaphore Flag Update Pulse (OE or SEM)15 ____ 15 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 35 ____ 45 ____ 65 ns 2943 tbl 11 |
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