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DS21Q50L Datasheet(PDF) 7 Page - Maxim Integrated Products |
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DS21Q50L Datasheet(HTML) 7 Page - Maxim Integrated Products |
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7 / 87 page  DS21Q50 7 of 87 Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125µs frame, there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1; time slot 1 is identical to channel 2; and so on. Each time slot (or channel) is made up of eight bits that are numbered 1 to 8. Bit number 1, MSB, is transmitted first. Bit number 8, the LSB, is transmitted last. The term “locked” is used to refer to two clock signals that are phase-locked or frequency-locked or derived from a common clock (i.e., a 8.192MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component). Throughout this data sheet, the following abbreviations are used: NAME FUNCTION FAS Frame Alignment Signal CAS Channel Associated Signaling MF Multiframe Si International bits CRC4 Cyclical Redundancy Check CCS Common Channel Signaling Sa Additional bits E-Bit CRC4 Error Bits LOC Loss of Clock TCLK This generally refers to the transmit rate clock and can reference an actual input signal to the device (TCLK) or an internally derived signal used for transmission. RCLK This generally refers to the recovered network clock and can be a reference to an actual output signal from the device or an internal signal. |
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