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DS2151 Datasheet(PDF) 5 Page - Dallas Semiconductor |
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DS2151 Datasheet(HTML) 5 Page - Dallas Semiconductor |
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5 / 51 page  DS2151Q 5 of 51 PIN SYMBOL TYPE DESCRIPTION 19 ACLKI I Alternate Clock Input. Upon a receive carrier loss, the clock applied at this pin (normally 1.544 MHz) will be routed to the RCLK pin. If no clock is routed to this pin, then it should be tied to DVSS VIA A1K Ohm RESISTOR. 20 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins assume the function listed in parenthesis (). 21 22 RTIP RRING - Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects to a 1:1 transformer (see Section 12 for details). 23 RVDD - Receive Analog Positive Supply. 5.0 volts. Should be tied to DVDD and TVDD pins. 24 RVSS - Receive Signal Ground. 0.0 volts. Should be tied to local ground plane 25 26 XTAL1 XTAL2 - Crystal Connections. A pullable 6.176 MHz crystal must be applied to these pins. See Section 12 for crystal specifications. 27 INT1 O Receive Alarm Interrupt 1. Flags host controller during alarm conditions defined in Status Register 1. Active low, open drain output. 28 INT2 O Receive Alarm Interrupt 2. Flags host controller during conditions defined in Status Register 2. Active low, open drain output. 29 TTIP - Transmit Tip. Analog line driver output; connects to a step-up transformer (see Section 12 for details). 30 TVSS - Transmit Signal Ground. 0.0 volts. Should be tied to local ground plane. 31 TVDD - Transmit Analog Positive Supply. 5.0 volts. Should be tied to DVDD and RVDD pins. 32 TRING - Transmit Ring. Analog line driver outputs; connects to a step-up transformer (see Section 12 for details). 33 TCHBLK O Transmit Channel Block. A user programmable output that can be forced high or low during any of the 24 T1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional T1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual channels in drop-and- insert applications. See Section 13 for timing details. 34 TLCLK O Transmit Link Clock. 4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See Section 13 for timing details. 35 TLINK I Transmit Link Data. If enabled via TCR1.2, this pin will be sampled during the F-bit time on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs bit position (D4) or the Z-bit position (ZBTSI). See Section 13 for timing details. 36 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling frames. See Section 13 for timing details. 37 DVDD - Digital Positive Supply. 5.0 volts. Should be tied to RVDD and TVDD pins. |
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