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7028L15PFGI8 Datasheet(PDF) 6 Page - Integrated Device Technology |
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7028L15PFGI8 Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 18 page 6 IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing of Power-Up Power-Down Waveform of Read Cycles(5) NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. 6. Refer to Chip Enable Truth Table. AC Test Conditions Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig. Figure 1. AC Output Test Load 4836 drw 04 893 Ω 30pF 347 Ω 5V DATAOUT BUSY INT 893 Ω 5pF* 347 Ω 5V DATAOUT 4836 drw 03 tRC R/ W CE ADDR tAA OE UB, LB 4836 drw 05 (4) tACE (4) tAOE (4) tABE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATAOUT BUSYOUT VALID DATA (4) (6) CE 4836 drw 06 tPU ICC ISB tPD (6) 50% 50% . Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1 and 2 4836 tbl 11 |
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