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70T3719MS166BBG Datasheet(PDF) 5 Page - Integrated Device Technology |
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70T3719MS166BBG Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 23 page  6.42 IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Commercial Temperature Range 5 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = X. 3. OE and ZZ are asynchronous input signals. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. Truth Table I—Read/Write and Enable Control (1,2,3,4) OE CLK CE0 CE1 BE3 BE2 BE1 BE0 R/W ZZ Byte 3 I/O27-35 Byte 2 I/O18-26 Byte 1 I/O9-17 Byte 0 I/O0-8 MODE X ↑ H L XXXX X L High-Z High-Z High-Z High-Z Deselected–Power Down X ↑ L L XXXX X X Active Active Active Active Not Allowed X ↑ H H XXXX X X Active Active Active Active Not Allowed X ↑ L H H H H H X L High-Z High-Z High-Z High-Z All Bytes Deselected X ↑ L H H H H L L L High-Z High-Z High-Z DIN Write to Byte 0 Only X ↑ L H H H L H L L High-Z High-Z DIN High-Z Write to Byte 1 Only X ↑ LH H L H H L L High-Z DIN High-Z High-Z Write to Byte 2 Only X ↑ LH LH H H L L DIN High-Z High-Z High-Z Write to Byte 3 Only X ↑ L H H H L L L L High-Z High-Z DIN DIN Write to Lower 2 Bytes Only X ↑ LH L L H H L L DIN DIN High-Z High-Z Write to Upper 2 bytes Only X ↑ L H LLLL L L DIN DIN DIN DIN Write to All Bytes L ↑ L H H H H L H L High-Z High-Z High-Z DOUT Read Byte 0 Only L ↑ L H H H L H H L High-Z High-Z DOUT High-Z Read Byte 1 Only L ↑ LH H L H H H L High-Z DOUT High-Z High-Z Read Byte 2 Only L ↑ LH LH H H H L DOUT High-Z High-Z High-Z Read Byte 3 Only L ↑ L H H H L L H L High-Z High-Z DOUT DOUT Read Lower 2 Bytes Only L ↑ LH L L H H H L DOUT DOUT High-Z High-Z Read Upper 2 Bytes Only L ↑ L H LLLLH L DOUT DOUT DOUT DOUT Read All Bytes H ↑ XXXXXX X L High-Z High-Z High-Z High-Z Outputs Disabled XXXXXXXX X H High-Z High-Z High-Z High-Z Sleep Mode 5682 tbl 02 Truth Table II—Address Counter Control (1,2) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. 7. Address A19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000H through 7FFFFH the value of a A19 is 0, while for physical addresses 80000H through FFFFFH the value of A19 is 1. The user needs to keep track of the device counter and make sure that A19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter operation and that A19 is in the appropriate state when using the REPEAT function. Address Previous Internal Address Internal Address Used CLK ADS CNTEN REPEAT(6) I/O(3) MODE An X An ↑ L(4) XH DI/O (n) External Address Used XAn An + 1 ↑ H L(5) HDI/O(n+1) Counter Enabled—Internal Address generation(7) XAn + 1 An + 1 ↑ HH H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) XX An ↑ XX L(4) DI/O(n) Counter Set to last valid ADS load 5682 tbl 03 |
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