70V3569S6BFGI8 datasheet(2/17 Pages) IDT

Part #	70V3569S6BFGI8

Description	HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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2 / 17 page

6.42

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

2

Description:

TheIDT70V3569isahigh-speed16Kx36bitsynchronousDual-Port

RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneousaccessofanyaddressfrombothports.Registersoncontrol,

data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming

latitudeprovidedbythisapproachallowssystemstobedesignedwithvery

shortcycletimes.Withaninputdataregister,theIDT70V3569hasbeen

optimizedforapplicationshavingunidirectionalorbidirectionaldataflow

inbursts.Anautomaticpowerdownfeature,controlledbyCE0andCE1,

permitstheon-chipcircuitryofeachporttoenteraverylowstandbypower

mode.

The 70V3569 can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power

supply for the core of the device (VDD) remains at 3.3V.

Pin Configuration(1,2,3,4)

NOTES:

1. All VDD pins must be connected to 3.3V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to VIL (0V).

3. All VSS pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

A17

VSS

B17

I/O15R

C17

VSS

D17

I/O14R

E16

VSS

E17

I/O13L

D16

I/O14L

C16

I/O15L

B16

I/O16L

A16

I/O17L

A15

OPTL

B15

VDDQR

C15

I/O16R

D15

VDDQL

E15

I/O13R

E14

I/O12L

D14

I/O17R

D13

VDD

C12

A6L

C14

VDD

B14

VSS

A14

A0L

A12

CNTENL

B12

A5L

C11

R/

WL

D12

A3L

D11

CNTRSTL

C10

VSS

B11

ADSL

A11

CLKL

D8

BE0L

C8

BE3L

A9

BE1L

D9

VDD

C9

CE1L

B9

CE0L

D10

OEL

C7

A10L

B8

BE2L

A8

A8L

B13

A1L

A13

A4L

A10

VDD

D7

A7L

B7

A9L

B6

A13L

C6

NC

D6

A11L

B5

NC

C5

NC

D5

NC

B4

VSS

C4

VDD

D4

I/O20L

B3

I/O18R

C3

VDDQR

D3

I/O21L

D2

VSS

C2

I/O19R

B2

VSS

B1

I/O20R

C1

VDDQL

D1

I/O22L

E1

I/O23L

E2

I/O22R

E3

VDDQR

E4

I/O21R

F1

VDDQL

F2

I/O23R

F3

I/O24L

F4

VSS

G1

I/O26L

G2

VSS

G3

I/O25L

G4

I/O24R

H1

VDD

H2

I/O26R

H3

VDDQR

H4

I/O25R

J1

VDDQL

J2

VDD

J3

VSS

J4

VSS

K1

I/O28R

K2

VSS

K3

I/O27R

K4

VSS

L1

I/O29R

L2

I/O28L

L3

VDDQR

L4

I/O27L

M1

VDDQL

M2

I/O29L

M3

I/O30R

M4

VSS

N1

I/O31L

N2

VSS

N3

I/O31R

N4

I/O30L

P1

I/O32R

P2

I/O32L

P3

VDDQR

P4

I/O35R

R1

VSS

R2

I/O33L

R3

I/O34R

R4

NC

T1

I/O33R

T2

I/O34L

T3

VDDQL

T4

VSS

U1

VSS

U2

I/O35L

U3

VDD

U4

NC

P5

NC

R5

NC

U6

A11R

P12

CNTENR

P8

A8R

U10

OER

P9

BE1R

R8

BE2R

T8

BE3R

U9

VDD

P10

VDD

T11

R/

WR

U8

BE0R

P11

CLKR

R12

A5R

T12

A6R

U12

A3R

P13

A4R

P7

A12R

R13

A1R

T13

A2R

U13

A0R

R6

A13R

T5

NC

U7

A7R

U14

VDD

T14

VSS

R14

VSS

P14

I/O2L

P15

I/O3L

R15

VDDQL

T15

I/O0R

U15

OPTR

U16

I/O0L

U17

I/O1L

T16

VSS

T17

I/O2R

R17

VDDQR

R16

I/O1R

P17

I/O4L

P16

VSS

N17

I/O5L

N16

I/O4R

N15

VDDQL

N14

I/O3R

M17

VDDQR

M16

I/O5R

M15

I/O6L

M14

VSS

L17

I/O8L

L16

VSS

L15

I/O7L

L14

I/O6R

K17

VSS

K16

I/O8R

K15

VDDQL

K14

I/O7R

J17

VDDQR

J16

VSS

J15

VDD

J14

VSS

H17

I/O10R

H16

VSS

H15

IO9R

H14

VDD

G17

I/O11R

G16

I/O10L

G15

VDDQL

G14

I/O9L

F17

VDDQR

F16

I/O11L

F14

VSS

70V3569BF

BF-208(5)

208-Pin fpBGA

Top View(6)

F15

I/O12R

R9

CE0R

R11

ADSR

T6

NC

T9

CE1R

B10

VSS

C13

A2L

P6

NC

R10

VSS

R7

A9R

T10

VSS

T7

A10R

U5

NC

4831 drw 02c

,

A7

A12L

A5

NC

A4

NC

A3

VSS

A2

IO18L

A1

IO19L

A6

NC

12/12/01

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